1. Field of the Invention
The present invention relates to clock synchronization and clock domain crossing, and more particularly to determining peak phase error between clock signals provided to different clock domains.
2. Description of the Related Art
Integrated circuit design continues to advance as increased functionality is packed into shrinking circuit configurations. Different clock frequencies are used to maximize circuit efficiency for disparate circuit functions. A typical microprocessor, for example, has different clock frequencies for different circuits within different clock domains, such as a processor clock, and input/output (I/O) clock, a core clock, a bus clock, a quad-pumped clock, etc. Information must be successfully transferred between different clock domains for proper chip operation. Clock domain crossing occurs when data or information generated by a circuit within a first clock domain driven by a first clock having a first frequency is transferred to or otherwise captured by a circuit within a second clock domain driven by a second clock with a second, different frequency. In many configurations, the disparate clock frequencies are derived from a common reference clock. Multiple phase-locked loop (PLL) circuits are used to multiply the frequency of a reference clock to generate the desired clock signals based on respective clock multipliers as understood by those skilled in the art. Ideally each PLL circuit produces a higher frequency clock signal synchronized with the reference clock within an acceptable tolerance range. As long as the clocks are synchronized within the acceptable tolerance range, such as, for example, within one-half cycle of the faster clock signal, data and information can be successfully transferred between circuits within different clock domains.
Marginal or even improper PLL circuit design may, however, jeopardize successful clock domain crossing causing failure of operation. Also, although a properly designed PLL circuit may function properly for most conditions, circuit variations and environmental conditions, such as voltage, temperature, speed, input jitter, etc., may result in improper operation and/or circuit failure. It is desired to quantify peak phase error between different clock signals derived from a common reference clock signal. The measured phase error during test identifies potential problems and enables circuit adjustment to resolve potential timing problems to achieve desired performance and operation. PLL circuits, for example, may be adjusted to minimize phase error and ensure proper operation for expected environmental conditions and variations.